1. Field of the Invention
The present invention relates to a processor system in which a synchronous dynamic memory is used in a storage apparatus for storing data or instructions.
2. Description of the Prior Art
In a conventional processor system, the main storage apparatus for storing data or instructions has been constructed by using a cheap, general purpose dynamic memory. An example of a general architecture of a main storage apparatus of work station using a plurality of dynamic memories can be seen in, for example, L. Johnson et al., xe2x80x9cSystem Level ASIC Design for Hewlett-Packard""s Low Cost PA-RISC Workstationsxe2x80x9d, ICCD ""91,International Conference on Computer Design, Proceeding, pp. 132-133.
Specifications of such a general purpose dynamic memory are seen in Hitachi IC Memory Handbook 2, xe2x80x9cDRAM, DRAM Modulexe2x80x9d(""91.9), pp.389-393. As will be seen from the above, the conventional dynamic memory does not have a clock input which serves as an input signal to a chip and during read/write, an internal operation clock was generated in the chip from other control input signals. Further, a mode register for prescribing the operation mode of the dynamic memory was not provided therein and as a consequence, the operation mode of the conventional dynamic memory was fundamentally single. Moreover, the dynamic memory was constructed of a single internal bank.
On the other hand NIKKEI ELECTRONICS, 1992. 5.11 (No. 553), pp. 143-147 introduces, as a dynamic memory being accessible at a twice or 4 times higher speed than before, a synchronous dynamic memory having a plurality of banks and a built-in register which can set the operation mode of these banks (such as delay from /RAS transition or /CAS transition, the number of words accessible sequentially (wrap length), and the order of addresses of input/output data pieces which are accessed sequentially).
In the processor system in which the main storage apparatus is constructed of general purpose dynamic memories without clock input as described above, it is impossible to input a clock signal directly to the respective dynamic memory chips and cause each chip to be operated in synchronism with the clock signal.
Accordingly, control signals for the general purpose dynamic memory must be prepared externally of the chip at a timing which meets an AC characteristic of the chip, on the basis of a system clock of the processor system.
Inside the general purpose dynamic memory, on the other hand, an internal operation clock was also generated from the control signal to ensure control of the internal operation. Consequently, in the processor system using the general purpose dynamic memories, the overhead covering the system clock up to the internal operation clock was increased, making it difficult to construct a main storage apparatus capable of operating at a high speed in synchronism with the system clock.
Further, in the processor system in which the main storage apparatus was constructed of general purpose dynamic memories of single mode not incorporating a mode register for prescribing the operation mode of the dynamic memory, the main storage needed to be set up so as to comply with a mode of the general purpose dynamic memory and it was difficult from the standpoint of performance and costs to construct a main storage apparatus optimized for the processor system.
Furthermore, in the processor system in which the main storage apparatus was constructed of general purpose dynamic memories incorporating a single bank, in order for the main storage apparatus to incorporate a plurality of banks, a plurality of general purpose dynamic memories were needed correspondingly and it was difficult from the standpoint of performance and costs to construct a main storage apparatus optimized for the processor system.
Under the circumstances, by using in the main storage apparatus a synchronous dynamic memory having a plurality of banks and a built-in register which can set the operation mode of the dynamic memory, the above problems can be solved.
On the other hand, the conventional processor premises that the main storage apparatus is constructed of general purpose dynamic memories incorporating a single bank. Therefore, if a synchronous dynamic memory having a plurality banks and whose operation mode is set by a built-in register is practically used in the main storage apparatus, then there arises a problem that any of the conventional processor and the synchronous dynamic memory lacks concrete means to realize controlling of access to the plurality of banks and controlling of setting of an operation mode to the built-in register. If the concrete means is arranged in any of the conventional processor and the synchronous dynamic memory, there arises a problem that the processor or the synchronous dynamic memory cannot have compatibility with high generality.
An object of the present invention is to solve the above problems and provide a processor system having a main storage apparatus which can be optimized from the standpoint of performance and costs.
To accomplish the above object, a processor according to a typical embodiment form of the present invention comprises:
a processor (MPU);
a main storage apparatus (MS) accessible by an address from the processor (MPU); and
a main storage controller (MC) coupled to the processor and the main storage apparatus,
the main storage apparatus (MS) is a memory (501) having a plurality of memory banks (502, 503) and a mode register (505) for determining an operation mode, and
the main storage controller (104) includes:
a register control unit (702) for detecting that the address from the processor (MPU) accesses the mode register (505) of the memory (501) and transferring setting information, occurring upon the accessing, to the mode register (505) of the memory (501) in response to a result of detection;
address registers (705a, 705b) for storing at least two consecutive preceding and succeeding access addresses from the processor (MPU);
a bank field comparator (714) for comparing pieces of information about bank fields of the respective two access addresses stored in the address registers, and
a memory access control unit (707) for delivering a bank operation start signal (/RAS0, /RAS1) for requesting parallel operations of two accesses corresponding to the two access addresses, in response to an output of the bank field comparator (714) when the bank field information pieces are different from each other. In a preferred embodiment form of the present invention, the processor (MPU) and the main storage controller (104) are individual chips.
In another preferred embodiment form of the present invention, the processor (MPU) and the main storage controller (104) are respectively formed of independent cores inside the same chip.
Further, in a concrete embodiment form of the present invention, when the bank field information pieces of the two access addresses are different from each other during the two preceding and succeeding accesses, during read operation of data by the preceding access from one (502) of the plurality of memory banks (502, 503) of the memory (501), access by the succeeding access to the other (503) of the plurality of memory banks (502, 503) of the memory (501) is initiated.
In a more concrete embodiment form of the present invention, the memory (501) is a synchronous dynamic memory which operates in synchronism with a clock signal applied to its clock input terminal.
Thus, since in accordance with the typical embodiment form of the present invention the means to realize controlling of access to a plurality of banks of the memory (MS) and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller (MC) coupled to the processor (MPU) and the main storage apparatus (MS), the use of the conventional processor of high generality and the conventional memory of high generality can be ensured.
Further, in a preferred embodiment form of the present invention, the processor (MPU) and the main storage controller (104) are respectively formed of separate chips and therefore the use of the conventional processor of high generality and the conventional memory chip of high generality can be ensured by adding the main storage controller (MC).
Further, in another preferred embodiment form of the present invention, the processor (MPU) and the main storage controller (104) are respectively formed of independent cores inside the same chip and therefore the use of the conventional processor core of high generality and the conventional memory chip of high generality can be ensured by adding a core of the main storage controller (MC) into the same chip.
Other objects and features of the present invention will become apparent from embodiments to be described hereinafter.